Bus signals
All five slots of the bus board carry the same 64-pin rosco_m68k expansion bus, wired pin for pin. This page explains what each signal does, for anyone designing a card or tracing a fault. For the pin grid as seen on the board, see the pinout at the end of the build guide.
The descriptions below are for the rosco_m68k r2 main board with the MC68010. Signal names are as printed on the bus board.
What the bus board is, and is not
The bus board is passive: copper tracks, the power section and nothing else. There are no buffers, drivers or terminators between the slots. Every signal on the bus comes straight from the CPU or the glue logic on the main board.
That has three consequences for card designers:
- Every card adds load. The main board's outputs have little current to spare. Use CMOS or HCT inputs, and buffer on the card if it puts several inputs on one line.
- Never drive an LED from a bus line. Use a transistor, or let the pin sink the current.
- Shared lines must be shared politely. Open-collector lines are only ever pulled low, never driven high (see below).
Which slot
The slots are electrically identical, so any card works in any slot. The board design marks BUS5, the slot at the far right, furthest from the power section, as the recommended slot for the main board.
Never plug or unplug a card with the power on.
Signal reference
Direction is seen from the main board: out is driven by the main board, in is driven by a card.
| Signal | Pins | Active | Direction | What it does |
|---|---|---|---|---|
| VCC | 2 | — | — | +5 V supply for every card. See Power and jumpers. |
| GND | 6 | — | — | Ground. |
| CLK | 4 | — | out | System clock, 10 MHz, 50 % duty cycle. |
| A1–A23 | 1, 3, 5 … 45 (odd) | high | out | Address bus. There is no A0: the CPU selects bytes with UDS and LDS. |
| D0–D15 | 38–64, see the pinout | high | in/out | Data bus, 16 bits. |
| AS | 47 | low | out | Address strobe: the address on A1–A23 is valid. |
| RW | 59 | — | out | Read/write: high for a read, low for a write. |
| UDS | 34 | low | out | Upper data strobe: the cycle uses D8–D15 (even byte). |
| LDS | 32 | low | out | Lower data strobe: the cycle uses D0–D7 (odd byte). |
| DTACK | 57 | low | in | Data transfer acknowledge: the card has put data on the bus or taken it. The CPU waits until it sees DTACK. |
| BERR | 49 | low | in | Bus error: ends the cycle with an exception instead of data. |
| FC0–FC2 | 20, 22, 24 | high | out | Function codes: user or supervisor, program or data. All three high means an interrupt acknowledge cycle. |
| IOSEL | 16 | low | out | From the main board's address decoder: the CPU is accessing I/O space. |
| EXPSEL | 18 | low | out | From the main board's address decoder: the CPU is accessing expansion memory space. |
| MFPIEO | 14 | low | in | On the r2 main board: interrupt request, level 3. The name dates from the r1 boards, where this pin was the MC68901's interrupt-enable output. |
| IPL0 | 26 | low | in | On the r2 main board: interrupt request, level 5. |
| IPL1 | 28 | low | in | On the r2 main board: interrupt request, level 2. |
| IPL2 | 30 | low | in | On the r2 main board: interrupt request, level 6. |
| RESET | 36 | low | in/out | System reset. The main board resets the bus at power-on; a card may pull it low to reset the system. |
| BR | 55 | low | in | Bus request: a card asks to take over the bus. |
| BG | 51 | low | out | Bus grant: the CPU will release the bus at the end of the current cycle. |
| BGACK | 53 | low | in | Bus grant acknowledge: the card now owns the bus. |
| VPA | 8 | low | in | Valid peripheral address: starts a slow 6800-style cycle timed by E, or asks for an autovector during an interrupt acknowledge. |
| E | 10 | — | out | Clock for 6800-family peripherals, one tenth of CLK. |
| VMA | 12 | low | out | Valid memory address, for 6800-family peripherals, in step with E. |
Open-collector lines
The interrupt lines (pins 14, 26, 28, 30) and RESET (pin 36) are shared by every card. Each has a pull-up on the main board: 4.7 kΩ on the interrupt lines. VPA (pin 8) has a 10 kΩ pull-up.
- Pull these lines low only through an open-collector or open-drain output, never with a normal totem-pole output.
- Never drive them high: a card driving high while another pulls low is a short circuit.
- Do not add your own pull-ups: the ones on the main board are enough.
Interrupts
A card requests an interrupt by pulling its line low and holding it until the CPU acknowledges. In the acknowledge cycle FC0–FC2 are all high, and A1–A3 carry the level being acknowledged. The card then answers in one of two ways:
- Vectored: put a vector number on D0–D7 and assert DTACK.
- Autovectored: assert VPA instead; the CPU uses the fixed vector for that level.
A card must check that A1–A3 match its own level before it answers. Several cards can share one level, but then each must also know whether it was the one asking.
Before choosing a level, check which levels the cards you already have use: see the memory map and IRQ table in the rosco_m68k hardware projects. Level 7 cannot be masked: keep it for things that really need it.
Taking over the bus
A card that wants to drive the bus itself, for example for DMA, uses BR, BG and BGACK:
- The card pulls BR low.
- The CPU answers with BG.
- When AS is high, the card pulls BGACK low, releases BR, and drives the bus.
- When done, the card stops driving the bus and releases BGACK.
While a card owns the bus, the CPU's address, data and control outputs are in high impedance.
6800-family peripherals
VPA, E and VMA let the 68010 talk to old 6800 peripherals. A card asserts VPA; the CPU then runs a slow cycle in step with E and asserts VMA when the address is valid. These cycles are much longer than normal ones, so use them only for chips that need them.
Address decoding
IOSEL and EXPSEL come from the main board's address decoder and are the easy way for a card to know which part of the address space is being accessed. A card still decodes the address lines within that space, so that it answers only at its own addresses and never on top of the main board or another card.
EXT lines: the 2×8 header
The 2×8 header below each slot carries 16 spare lines, EXT1 to EXT16. Odd numbers are in the left row, EXT1 at the top, as on the 2×32 header.
The EXT lines join the five slots pin for pin and go nowhere else: not to the main board, not to power. Cards can use them to talk to each other without taking bus lines, for example to pass a private interrupt or a chip select. There is no standard for their use: if two cards both use one line, they must agree on what it means.