How it works

The RAM expansion is a small, simple card: eight memory chips, one programmed logic chip and one transistor. This page walks through what each part does. It helps when you are tracing a fault, or want to build something similar.

Signals the card uses#

The card uses only part of the 64-pin expansion bus:

It does not use DTACK, interrupts, the clock or anything else. In particular, it never tells the CPU that it has finished: the main board does that (see below).

The memory chips#

U1–U8 are AS6C4008 static RAMs, 512 K × 8 bits each: the same chip as on the main board. Static RAM keeps its contents as long as it has power, with no refresh, and answers in 55 ns.

The 68010 has a 16-bit data bus, so the chips work in pairs. In each pair, one chip holds the odd bytes (D0–D7, selected by LDS) and the other the even bytes (D8–D15, selected by UDS). Together a pair makes 1 MB.

With the board turned as on the build guide maps (J1 on the right), the pairs run from right to left: U1 and U2 next to J1, U7 and U8 at the far left. In each pair the odd chip is in the top row.

The address lines reach the chips in a mixed order, not A1 to pin A0 and so on. That does not matter for RAM: each address still reaches exactly one memory cell, always the same one.

The decoder (IC1)#

IC1 is an ATF16V8 programmable logic chip. It has eight outputs, one chip select for each memory chip, and it pulls one or two of them low when all of these are true:

• EXPSEL is low: the CPU is accessing expansion space.
• A20–A23, the megabyte number, fall inside this card's 4 MB, given the base set by JP1–JP3.
• LDS is low (for the odd chip of the pair) or UDS is low (for the even chip). A 16-bit access selects both chips.

Everything else is ignored, so the card stays silent outside its own 4 MB. The jumper settings are explained in Address jumpers and memory map.

JP1–JP3 each pull an IC1 input up to 5 V when a cap is fitted. Without a cap, a 4K7 resistor (R3–R5) holds the input at 0 V.

IC1 must be programmed with the card's decoder logic before it goes in. A blank ATF16V8, or one programmed for something else, does nothing useful here.

Reading and writing (Q1)#

Each memory chip has two control inputs besides chip select: write enable and output enable. Both are active low.

• Write enable comes straight from RW: low means write.
• Output enable needs the opposite: low means read. Q1, a 2N3904 transistor, makes it. When RW goes high (read), Q1 switches on through R2 (100K) and pulls output enable low. When RW is low (write), Q1 is off and R1 (10K) pulls output enable high.

So a chip only drives the data bus while it is selected and the CPU is reading. That is why Q1 turned round breaks every read: writes still happen, but nothing comes back.

Why the main board supplies DTACK#

On the 68010, every bus cycle waits until something answers with DTACK. This card does not have that line. The 55 ns chips are fast enough to answer without the CPU having to wait, so the original design leaves the answer to the main board: with JP4 on the main board shorted, the main board asserts DTACK for every access to expansion space.

With JP4 open, nobody answers, the main board's watchdog ends the cycle with a bus error, and the firmware sees no memory. See Address jumpers and memory map.

Power and decoupling#

Each memory chip and IC1 has its own 100 nF capacitor (C1–C9), to absorb the short current spikes when a chip switches. C10 and C11 (100 µF) are the card's local reservoir, one at each end of J1. The card draws its 5 V from pin 2 of the bus.

Fewer chips: 1, 2 or 3 MB#

The card works with fewer than eight chips, which is why the board says 1/2/3/4MB. Fit chips in whole pairs, starting from U1 and U2:

The decoder does not need to know: it still selects the empty sockets, but no chip drives the data there, the test value does not come back, and the firmware stops counting at the first empty pair. A gap, for example U1–U2 and U5–U6 without U3–U4, cuts the count at the gap.

J1 is mirrored#

The card hangs component side down from the 2×32 pins of the main board or a bus board slot. Because it is turned over, the pin numbers of its own connector J1 are mirrored against the bus: the card's pin 1 meets bus pin 2 (VCC), and so on. Fitted the right way round, everything lines up. Turned the wrong way, 5 V lands on an address line, which is why the build guide insists on the beep test before the first power-on.